\ SSP1600.DEF instruction definition file for SSP1600 \ SSP1600 Copyright SAMSUNG SEMICONDUCTOR INC. 1992 12/03/92 \ \ Initial Release: ??/??/?? FF00 ROMSIZE 0 01FF RAMRANGE WORD-HILOW \ sixteen bit processor \ System Registers END-EQUATES \ Register and Addressing Mode Definitions $ARRAY wrregs 000 ,$ - 001 ,$ X 002 ,$ Y 003 ,$ A 004 ,$ ST 005 ,$ STACK 006 ,$ PC 007 ,$ P 008 ,$ EXT0 009 ,$ EXT1 00A ,$ EXT2 00B ,$ EXT3 00C ,$ EXT4 00D ,$ EXT5 00E ,$ EXT6 00F ,$ EXT7 $; $ARRAY opregs 0 ,$ ROR 1 ,$ ROL 2 ,$ SHR 3 ,$ SHL 4 ,$ INC 5 ,$ DEC 6 ,$ NEG 7 ,$ ABS $; $ARRAY opregs2 2 ,$ RESL 3 ,$ SETL 4 ,$ RESIE 5 ,$ SETIE 8 ,$ RESOP 9 ,$ SETOP $; $ARRAY ccregs 000 ,$ ALWAYS 020 ,$ USR0=0 030 ,$ USR1=0 040 ,$ LINK=0 050 ,$ Z=0 060 ,$ OV=0 070 ,$ N=0 120 ,$ USR0=1 130 ,$ USR1=1 140 ,$ LINK=1 150 ,$ Z=1 160 ,$ OV=1 170 ,$ N=1 $; $ARRAY cdregs 000 ,$ C 001 ,$ D 000 ,$ 0 001 ,$ 1 $; $ARRAY ptregs 000 ,$ R0 001 ,$ R1 002 ,$ R2 003 ,$ R3 100 ,$ R4 101 ,$ R5 102 ,$ R6 103 ,$ R7 $; $ARRAY ptregs() 000 ,$ (R0) 001 ,$ (R1) 002 ,$ (R2) 003 ,$ (R3) 100 ,$ (R4) 101 ,$ (R5) 102 ,$ (R6) 103 ,$ (R7) 00C ,$ (R0+) 00D ,$ (R1+) 00E ,$ (R2+) 00F ,$ (R3|11) 10C ,$ (R4+) 10D ,$ (R5+) 10E ,$ (R6+) 10F ,$ (R7|11) 008 ,$ (R0-) 009 ,$ (R1-) 00A ,$ (R2-) 00B ,$ (R3|10) 108 ,$ (R4-) 109 ,$ (R5-) 10A ,$ (R6-) 10B ,$ (R7|10) 004 ,$ (R0+!) 005 ,$ (R1+!) 006 ,$ (R2+!) 007 ,$ (R3|01) 104 ,$ (R4+!) 105 ,$ (R5+!) 106 ,$ (R6+!) 107 ,$ (R7|01) 003 ,$ (R3|00) 103 ,$ (R7|00) $; $ARRAY miregs() 000 ,$ (R0) 001 ,$ (R1) 002 ,$ (R2) 003 ,$ (R3) 00C ,$ (R0+) 00D ,$ (R1+) 00E ,$ (R2+) 00F ,$ (R3|11) 008 ,$ (R0-) 009 ,$ (R1-) 00A ,$ (R2-) 00B ,$ (R3|10) 004 ,$ (R0+!) 005 ,$ (R1+!) 006 ,$ (R2+!) 007 ,$ (R3|01) 003 ,$ (R3|00) $; $ARRAY mjregs() 000 ,$ (R4) 001 ,$ (R5) 002 ,$ (R6) 003 ,$ (R7) 00C ,$ (R4+) 00D ,$ (R5+) 00E ,$ (R6+) 00F ,$ (R7|11) 008 ,$ (R4-) 009 ,$ (R5-) 00A ,$ (R6-) 00B ,$ (R7|10) 004 ,$ (R4+!) 005 ,$ (R5+!) 006 ,$ (R6+!) 007 ,$ (R7|01) 003 ,$ (R7|00) $; $ARRAY ptregs(()) 000 ,$ ((R0)) 001 ,$ ((R1)) 002 ,$ ((R2)) 003 ,$ ((R3)) 100 ,$ ((R4)) 101 ,$ ((R5)) 102 ,$ ((R6)) 103 ,$ ((R7)) 00C ,$ ((R0+)) 00D ,$ ((R1+)) 00E ,$ ((R2+)) 00F ,$ ((R3|11)) 10C ,$ ((R4+)) 10D ,$ ((R5+)) 10E ,$ ((R6+)) 10F ,$ ((R7|11)) 008 ,$ ((R0-)) 009 ,$ ((R1-)) 00A ,$ ((R2-)) 00B ,$ ((R3|10)) 108 ,$ ((R4-)) 109 ,$ ((R5-)) 10A ,$ ((R6-)) 10B ,$ ((R7|10)) 004 ,$ ((R0+!)) 005 ,$ ((R1+!)) 006 ,$ ((R2+!)) 007 ,$ ((R3|01)) 104 ,$ ((R4+!)) 105 ,$ ((R5+!)) 106 ,$ ((R6+!)) 107 ,$ ((R7|01)) 003 ,$ ((R3|00)) 103 ,$ ((R7|00)) $; \ Instruction Definitions I: ADD " A" , { ptregs ^*1 } [ 9200 @1 | 10 ] " A" , { ptregs() ^*1 } [ 8200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ 8A00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ 8000 @1 | 10 ] " A" , { *1 0 1FF ==} [ 8600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ 8600 @1 | 10 ] \ @ optional 1 I; I: ADDI " A" , { *1 0 FFFF ==} [ 8800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ 8800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ 9800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ 9800 @1 | 10 ] 2 I; I: AND " A" , { ptregs ^*1 } [ B200 @1 | 10 ] " A" , { ptregs() ^*1 } [ A200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ AA00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ A000 @1 | 10 ] " A" , { *1 0 1FF ==} [ A600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ A600 @1 | 10 ] \ @ optional 1 I; I: ANDI " A" , { *1 0 FFFF ==} [ A800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ A800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ B800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ B800 @1 | 10 ] 2 I; I: BRA { ccregs ^*1 } , " @" { *2 0 FFFF ==} [ 4C00 @1 | 10 ][ @2 00 ] { ccregs ^*1 } , { *2 0 FFFF ==} [ 4C00 @1 | 10 ][ @2 00 ] 2 I; I: CALL { ccregs ^*1 } , " @" { *2 0 FFFF ==} [ 4800 @1 | 10 ][ @2 00 ] { ccregs ^*1 } , { *2 0 FFFF ==} [ 4800 @1 | 10 ][ @2 00 ] 2 I; I: CMP " A" , { ptregs ^*1 } [ 7200 @1 | 10 ] " A" , { ptregs() ^*1 } [ 6200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ 6A00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ 6000 @1 | 10 ] " A" , { *1 0 1FF ==} [ 6600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ 6600 @1 | 10 ] \ @ optional 1 I; I: CMPI " A" , { *1 0 FFFF ==} [ 6800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ 6800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ 7800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ 7800 @1 | 10 ] 2 I; I: EOR " A" , { ptregs ^*1 } [ F200 @1 | 10 ] " A" , { ptregs() ^*1 } [ E200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ EA00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ E000 @1 | 10 ] " A" , { *1 0 1FF ==} [ E600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ E600 @1 | 10 ] \ @ optional 1 I; I: EORI " A" , { *1 0 FFFF ==} [ E800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ E800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ F800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ F800 @1 | 10 ] 2 I; I: LD { wrregs ^*1 } , " (A)" { 3 @1 - 1 FFFF ==}" LD A,(A) is illegal!" [ 4A00 @1 4 << | 10 ] { wrregs ^*1 } , { ptregs ^*2 } [ 1200 @2 | @1 4 << | 10 ] { wrregs ^*1 } , { ptregs() ^*2 } [ 0200 @2 | @1 4 << | 10 ] { wrregs ^*1 } , { ptregs(()) ^*2 } [ 0A00 @2 | @1 4 << | 10 ] " -" , " -" [ 0000 10 ] { wrregs ^*1 } , { wrregs ^*2 } { @1 @2 - 1 FFFF ==}" Source and destination cannot be the same!" [ 0000 @2 | @1 4 << | 10 ] { ptregs ^*1 } , { wrregs ^*2 } [ 1400 @1 | @2 4 << | 10 ] { ptregs() ^*1 } , { wrregs ^*2 } [ 0400 @1 | @2 4 << | 10 ] " A" , { *1 0 1FF ==} [ 0600 @1 | 10 ] { *1 0 1FF ==} , " A" [ 0E00 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ 0600 @1 | 10 ] \ @ optional " @" { *1 0 1FF ==} , " A" [ 0E00 @1 | 10 ] \ @ optional 1 I; I: LDI { ptregs() ^*1 } , { *2 0 FFFF ==} [ 0C00 @1 | 10 ][ @2 00 ] { wrregs ^*1 } , { *2 0 FFFF ==} [ 0800 @1 4 << | 10 ][ @2 00 ] { ptregs() ^*1 } , " @" { *2 0 FFFF ==|} [ 0C00 @1 | 10 ][ @2 00 ] { wrregs ^*1 } , " @" { *2 0 FFFF ==|} [ 0800 @1 4 << | 10 ][ @2 00 ] { ptregs ^*1 } , " @" { *2 0 01FF ==|} 1 # [ 1800 @1 3 & 8 << | @1 100 & 2 << | @2 | 10 ] { ptregs ^*1 } , { *2 0 01FF ==|} 1 # [ 1800 @1 3 & 8 << | @1 100 & 2 << | @2 | 10 ] 2 I; I: MLD { mjregs() ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ B600 @1 4 << | @2 | @3 8 << | 10 ] { wrregs ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ A400 @1 4 << | @2 | @3 8 << | 10 ] { mjregs() ^*1 } , { miregs() ^*2 } [ B600 @1 4 << | @2 | 100 | 10 ] { wrregs ^*1 } , { miregs() ^*2 } [ A400 @1 4 << | @2 | 10 ] 1 I; I: MOD { ccregs ^*1 } , { opregs ^*2 } [ 9000 @1 | @2 | 10 ] " F" , { opregs2 ^*2 } [ 9400 @2 | 10 ] 1 I; I: MPYA { mjregs() ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ 9600 @1 4 << | @2 | @3 8 << | 10 ] { wrregs ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ 8400 @1 4 << | @2 | @3 8 << | 10 ] { mjregs() ^*1 } , { miregs() ^*2 } [ 9600 @1 4 << | @2 | 100 | 10 ] { wrregs ^*1 } , { miregs() ^*2 } [ 8400 @1 4 << | @2 | 10 ] 1 I; I: MPYS { mjregs() ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ 3600 @1 4 << | @2 | @3 8 << | 10 ] { wrregs ^*1 } , { miregs() ^*2 } , { cdregs ^*3 } [ 2400 @1 4 << | @2 | @3 8 << | 10 ] { mjregs() ^*1 } , { miregs() ^*2 } [ 3600 @1 4 << | @2 | 100 | 10 ] { wrregs ^*1 } , { miregs() ^*2 } [ 2400 @1 4 << | @2 | 10 ] 1 I; I: OR " A" , { ptregs ^*1 } [ D200 @1 | 10 ] " A" , { ptregs() ^*1 } [ C200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ CA00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ C000 @1 | 10 ] " A" , { *1 0 1FF ==} [ C600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ C600 @1 | 10 ] \ @ optional 1 I; I: ORI " A" , { *1 0 FFFF ==} [ C800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ C800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ D800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ D800 @1 | 10 ] 2 I; I: RET [ 0065 10 ] 1 I; I: SUB " A" , { ptregs ^*1 } [ 3200 @1 | 10 ] " A" , { ptregs() ^*1 } [ 2200 @1 | 10 ] " A" , { ptregs(()) ^*1 } [ 2A00 @1 | 10 ] " A" , { wrregs ^*1 } { 3 @1 - 1 FFFF ==}" Source and destination cannot be the same!" [ 2000 @1 | 10 ] " A" , { *1 0 1FF ==} [ 2600 @1 | 10 ] " A" , " @" { *1 0 1FF ==|} [ 2600 @1 | 10 ] \ @ optional 1 I; I: SUBI " A" , { *1 0 FFFF ==} [ 2800 10 ][ @1 00 ] " A" , " @" { *1 0 FFFF ==|} [ 2800 10 ][ @1 00 ] \ @ optional " @" { *1 0 1FF ==|} 1 # [ 3800 @1 | 10 ] \ @ optional { *1 0 1FF ==|} 1 # [ 3800 @1 | 10 ] 2 I; I: DW { *1 |} [ @1 00 ] " @" { *1 |} [ @1 00 ] 1 I; \ REPEAT: \ { *1 |} [D @1 0 REP] \ " @" { *1 |} [D @1 0 REP] \ 1 I;